1. Field of the Invention
This invention relates generally to rate-change circuits for data transmission and, more particularly, to minimal delay fractional rate-change circuits utilized in time compression multiplex systems.
2. Description of the Prior Art
Rate changing in data transmission applications entails the transformation of data at one rate to data at another predefined rate. Although rate-change circuits are encountered in many data applications, particular attention is focused upon, as exemplary, time compression multiplex (TCM) systems utilizing dispersive channels.
Broadly described, the TCM (also known as burst mode) system comprises cricuitry arranged at each end of the channel for alternately sending bursts of data in multiple-sample blocks. A suitable guard band is associated with each burst to allow for dissipation of transients as well as synchronization and system clock recovery. Buffering in the form of rate-change circuits is required at each channel end to accumulate data for transmission whenever a particular end circuit is operating in the receive mode.
Under the TCM mode of data transmission, the round trip delay time is a critical parameter in controlling a signal interference, known as echo, which originates from effects of channel irregularities on signal propagation. A significant component in this overall delay has been excess delay, that is, the delay in emptying the last buffer are utilized in conventional rate-change circuits which change the rate from the primary (terminal) rate to the secondary (burst) rate and vice versa. Prior to 1971, zero excess delay had not been achieved with conventional arrangements of rate-change circuits, typically shift registers, unless the number of independent shift registers was increased to the number of bits in a block, thus demanding extremely complex arrangements of gating and shifting functions.
The most pertinent prior art regarding rate-change circuits having zero excess delay was set forth by the applicant in a paper entitled "A General Class of Rate-Change Circuits," published in The Bell System Technical Journal, December, 1971. The paper presented and discussed a circuit topology useful primarily in magnetic domain technology. The constraint imposed by the technology on the design of such circuits is that all the individual bits of information have to be propagated by one period in one clock cycle. To achieve this design requirement, the patterns of circuit paths are arranged in a geometric progression. The topological arrangement, if implemented with shift registers, would perform satisfactorily to yield zero excess delay. However, the topology imposes two unnecessary restrictions: (i) the capability of shift registers to shift in at one rate and shift out at another rate is not utilized; and (ii) fractional rate change is a 2-step procedure in this topology and therefore requires an excessive number of shift registers.